As promised when releasing 1.0, we’ve tried our best to keep the API stable. We think most designs will continue to compile with this new version, although special care needs to be taken when using:
..inline blackboxes. Instead of taking a single HDL, inline primitives now take multiple. For example,
InlinePrimitive VHDL ".."must now be written as
InlinePrimitive [VHDL] "..".
Unsigned, as they now respect their
maxBound. See #1089.
On top of that, we’ve added a number of new features:
makeTopEntity: Template Haskell function for generating TopEntity annotations. See the documentation on Haddock for more information.
Clash.Explicit.SimIO: ((System)Verilog only) I/O actions that can be translated to HDL I/O. See the documentation on Haddock for more information.
Clash.Class.AutoReg: A smart register that improves the chances of synthesis tools inferring clock-gated registers. See the documentation on Haddock for more information.
View all the changes in the CHANGELOG. Happy hacking!